1. Field of the Invention
The present invention relates to an integrated circuit design automation system for designing power-efficient integrated circuits. In particular, the present invention relates to a method used in conjunction with an integrated circuit design automation system that optimizes a power-efficient integrated circuit design by connecting appropriately placed and sized power-gated devices.
2. Discussion of the Related Art
In the advanced fabrication processes developed recently, the size of leakage currents1 has increased substantially over that of previous fabrication processes. Large leakage currents are detrimental in particular to battery-operated devices, such as cellular telephones and other wireless devices, which spend a substantial amount of time under stand-by operation conditions. To reduce power consumption during stand-by operations, many design techniques have been developed to minimize leakage current in an integrated circuit. One such technique, for example, is the “power-gating” technique, which is applicable to multi-threshold CMOS (“MTCMOS”) circuits. An MTCMOS circuit includes transistors of different threshold voltages. Specifically, the higher threshold PMOS and NMOS transistors are used as “switch” or “sleep” transistors, each of which selectively connects or disconnects its associated physical power supply (i.e., the power supply voltage or the ground reference voltage for the integrated circuit) to and from its associated CMOS logic circuits, which are built out of lower threshold voltage transistors for higher performance. (The physical power supplies are also referred to as primary or global power supplies.) In that application, the CMOS logic circuits are each connected in series to the ground reference voltage by one or more NMOS transistors and to the power supply voltage by one or more PMOS transistors. The voltage at a source terminal of a switch transistor is referred to as a “virtual power supply” to distinguish it from the physical power supplies of the integrated circuit. While this circuit configuration significantly reduces leakage currents, power-gating presents design challenges not seen in non-power gated integrated circuit designs. One challenge, for example, relates to the area overhead introduced by the switch transistors. Another challenge relates to the electrical effects introduced by the connecting logic circuit in series with switch transistors. 1 A leakage current is the actual current load in a device when the device is in the non-conducting state.
To minimize area overhead, switch transistors are often shared among multiple MTCMOS logic cells. While sharing switch transistors reduces silicon area, significant timing issues may arise that require extensive timing analysis and delay calculation to ensure proper operation. The timing issues result from the switching time degradation in a CMOS logic circuit when the CMOS logic circuit is powered through a switch transistor connecting it to the ground reference (i.e., the effective resistance to ground seen by the discharging load capacitor is increased). The extent of the switching time degradation depends on both the size of the switch transistor and the current in the switch transistor when the logic circuit switches. Thus, it is desirable to minimize both the resistance and the current in the switch transistor. Reducing the number of logic circuit transistors sharing a switch transistor reduces switching time degradation, but increases silicon area.
There is thus a need for a design method that maximizes switch transistor sharing while simultaneously avoiding switching time degradation.